1. Field of the Invention
The present invention relates to a transistor, and more particularly, to a transistor capable of improving short channel effect, and a method for manufacturing thereof.
2. Description of the Related Art
To achieve a higher integration of a semiconductor devices, the size of the semiconductor devices needs to be reduced. For example, a linewidth of a gate electrode in a metal oxide semiconductor field effect transistor (MOSFET) needs to be reduced, which also reduces the width of the channel of the MOSFET due to lateral diffusion of source/drain regions. However, as a result of reduced channel length, short channel effects increase.
FIG. 1 is a cross-sectional view illustrating a related art method for manufacturing a transistor.
Referring to FIG. 1, a layer of gate insulating material, a polysilicon layer, and a hard mask layer 40 are sequentially formed on a semiconductor substrate 10 in which a field oxide layer (not shown) with a predetermined height is formed in advance.
After hard mask 40 is patterned into a shape of a gate electrode, the polysilicon layer and the layer of gate insulating material are patterned into the shape of hard mask layer 40 by an etch process, to thereby form a gate 50 including gate dielectric 20 and gate electrode 30.
Thereafter, hard mask 40 may be removed and gate spacers 60 are formed on sidewalls of gate 50 by a conventional method. Then, impurities are implanted into the semiconductor substrate 10 using gate 50 and gate spacers 60 as a mask to form source/drain regions 70.
However, according to the related art method for manufacturing the transistor, there is a problem that an additional purchase of a device should be needed in order to fabricate the transistor.
In addition, as the gate length is reduced, a narrow line effect gives rise to problems such as formation of silicide contacts being difficult and gate resistance being higher.